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cy7c199cn 256 k (32 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06435 rev. *e revised march 17, 2011 features fast access time: 15 ns and 20 ns wide voltage range: 5.0v 10% (4.5v to 5.5v) cmos for optimum speed and power ttl-compatible inputs and outputs 2.0 v data retention low cmos standby power automated power down when deselected available in pb-free 28-pin tsop i, 28-pin molded soj and 28-pin dip packages general description [1] the cy7c199cn is a high performance cmos asynchronous sram organized as 32k by 8 bits that supports an asynchronous memory interface. the device features an automatic power down feature that reduces powe r consumption when deselected. see the ?truth table? on page 4 in this data sheet for a complete description of read and write modes. the cy7c199cn is available in pb-free 28-pin tsop i, 28-pin molded soj and 28-pin dip package(s). logic block diagram product portfolio ?15 ?20 unit maximum access time 15 20 ns maximum operating current 80 75 ma maximum cmos standby current (low power) 500 500 a row decoder ram array column decoder input buffer sense amps a x power down circuit i/ox oe we ce x [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 2 of 18 contents pin layout and specifications ........................................ 3 pin description ................................................................. 4 truth table ........................................................................ 4 maximum ratings ............................................................. 4 operating range ............................................................... 4 capacitance ........................................................................................ 5 thermal resistance ........................................................................ 5 dc electrical characteristics .......................................... 5 ac test loads .................................................................. 6 ac test conditions .......................................................... 6 ac electrical characteristics ..................................................... 7 data retention characteristics ................................................. 7 timing waveforms ........................................................... 8 data retention waveform ........................................... 8 read cycle 1 ............................................................... 8 read cycle 2 ........... .............. .............. .............. .......... 9 write cycle 1 (we controlled) ..............................................10 write cycle 2 (ce controlled) ...............................................11 write cycle 3 (we controlled, oe low) .............................12 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package diagrams .......................................................... 14 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc solutions ......................................................... 18 [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 3 of 18 pin layout and specifications a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 io 0 io 1 io 2 v ss io 3 io 4 io 5 io 6 io 7 ce a 0 oe a 1 a 2 a 3 a 4 we v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 28 dip a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 io 0 io 1 io 2 v ss io 3 io 4 io 5 io 6 io 7 ce a 0 oe a 1 a 2 a 3 a 4 we v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 28 soj oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 io 0 io 1 io 2 v ss io 3 io 4 io 5 io 6 io 7 ce a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 28 tsop i (8 x 13.4 mm) note 1. for best practices recommendations, refer to the cypress application note system design guidelines on www.cypress.com . [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 4 of 18 pin description pin type description dip soj tsop i a x input address inputs 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 28 ce control chip enable 20 20 27 io x input or output data input outputs 11, 12, 13, 15, 16, 17, 18, 19 11, 12, 13, 15, 16, 17, 18, 19 18, 19, 20, 22, 23, 24, 25, 26 oe control output enable 22 22 1 v cc supply power (5.0v) 28 28 7 v ss supply ground 14 14 21 we control write enable 27 27 6 truth table ce oe we iox mode power h x x high-z deselect/power down stand by (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high-z selected, outputs disabled active (i cc ) maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. parameter description value unit t stg storage temperature ?65 to +150 c t amb ambient temperature with power applied (that is, case temperature) ?55 to +125 c v cc core supply voltage relative to v ss ?0.5 to +7.0 v v in , v out dc voltage applied to any pin relative to v ss ?0.5 to v cc + 0.5 v i out output short-circuit current 20 ma v esd static discharge voltage (in accordance with mil-std-883, method 3015) > 2001 v i lu latch-up current > 200 ma operating range range ambient temperature (t a ) voltage range (v cc ) commercial 0c to 70c 5.0 v 10% industrial ?40c to 85c 5.0 v 10% [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 5 of 18 dc electrical characteristics over the operating range (?15, ?20) [2] parameter description condition ?15 ?20 unit min max min max v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage ?0.5 0.8 ?0.5 0.8 v v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 ? 0.4 v i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc ? 80 ? 75 ma i sb1 automatic ce power down current ttl inputs max v cc , ce v ih , v in v ih or v in v il , f = f max ? 30 ? 30 ma ? 10 ? 10 ma i sb2 automatic ce power down current cmos inputs max v cc , ce v cc ? 0.3 v, v in v cc ? 0.3 v, or v in 0.3 v, f = 0 ? 10 ? 10 ma ? 500 ? 500 a i oz output leakage current gnd v i v cc , output disabled ?5 +5 ?5 +5 a i ix input leakage current gnd v i v cc ?5 +5 ?5 +5 a capacitance [3] parameter description conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 5.0 v 8 pf c out output capacitance 8 thermal resistance [3] parameter description conditions tsop i soj dip unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 square inch, two?layer printed circuit board 88.6 79 69.33 c/w jc thermal resistance (junction to case) 21.94 41.42 31.62 note 2. v il (min) = ?2.0 v for pulse durations of less than 20 ns. [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 6 of 18 ac test loads ac test conditions parameter description nom unit c1 capacitor 1 30 pf c2 capacitor 2 5 r1 resistor 1 480 r2 resistor 2 255 r3 resistor 3 480 r4 resistor 4 255 r th resistor thevenin 167 v th voltage thevenin 1.73 v v cc v ss rise time 1 v/ns fall time 1 v/ns all input pulses 90% 10% 90% 10% v output r1 r2 c1 cc v output r3 c2 cc r4 output loads output loads for t hzoe ,t hzce &t hzwe * including scope and jig capacitance (b)* (a)* r th t v thevenin equivalent note 3. tested initially and after any design or process change that may affect these parameters. [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 7 of 18 ac electrical characteristics [4] parameter description ?15 ?20 unit min max min max t rc read cycle time 15 ? 20 ? ns t aa address to data valid ? 15 ? 20 ns t oha data hold from address change 3 ? 3 ? ns t ace ce to data valid ? 15 ? 20 ns t doe oe to data valid ? 7 ? 9 ns t lzoe oe to low-z [5] 0 ? 0 ? ns t hzoe oe to high-z [5, 6] ? 7 ? 9 ns t lzce ce to low-z [5] 3 ? 3 ? ns t hzce ce to high-z [5, 6] ? 7 ? 9 ns t pu ce to power up 0 ? 0 ? ns t pd ce to power down ? 15 ? 20 ns t wc write cycle time [7] 15 ? 20 ? ns t sce ce to write end 10 ? 15 ? ns t aw address setup to write end 10 ? 15 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 9 ? 15 ? ns t sd data setup to write end 9 ? 10 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high-z [5, 6] ? 7 ? 10 ns t lzwe we high to low-z [5] 3 ? 3 ? ns data retention characteristics [8] parameter description condition min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce v cc ? 0.3 v, v in v cc ? 0.3 v or v in 0.3 v ? 150 a t cdr chip deselect to data retention time 0 ? ns t r operation recovery time 200 ? s notes 4. test conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5 v, and input pulse levels o f 0 to 3.0 v. 5. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 6. t hzoe , t hzce , t hzwe are specified as in part (b) of the ?? on page 5 . transitions are measured 200 mv from steady state voltage. 7. the internal memory write time is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 8. l-version only. [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 8 of 18 timing waveforms data retention waveform read cycle 1 [9, 10] ce data retention mode t cdr t r v cc address data out previous data valid data valid t rc t aa t oha [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 9 of 18 read cycle 2 [11, 12] timing waveforms (continued) address ce oe data out data valid t rc high z t ace t hzce t hzoe t doe t lzoe t lzce v cc current i cc i sb t pu 50% 50% t pd high z notes 9. device is continuously selected. oe = v il = ce . 10. we is high for read cycle. 11. this cycle is oe controlled and we is high read cycle. 12. address valid before or similar with ce transition low. [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 10 of 18 write cycle 1 (we controlled) [13, 14, 15] timing waveforms (continued) address ce we data in/out t wc data-in valid t sce t sa t aw t pwe t ha t hd t sd oe t hzoe undefined see footnotes [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 11 of 18 write cycle 2 (ce controlled) [14, 16, 17] timing waveforms (continued) address ce we data in/out t wc data-in valid t sce t sa t aw t ha t hd t sd high z high z notes 13. this cycle is we controlled, oe is high during write. 14. data in and/or out is high impedance if oe = v ih . 15. during this period the ios are in output state and input signals must not be applied. 16. this cycle is ce controlled. 17. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 12 of 18 write cycle 3 (we controlled, oe low) [18] timing waveforms (continued) address ce we data in out t wc data in valid t sce t sa t aw t pwe t ha t hd t sd t hzwe t lzwe undefined see footnotes undefined see footnotes note 18. the cycle is we controlled, oe low. the minimum write cycl e time is the sum of t hzwe and t sd . [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 13 of 18 ordering information contact local sales representative regarding availability of these parts. speed (ns) ordering code package diagram package type power option operating range 15 cy7c199cn-15pxc 51-85014 28 dip (6.9 x 35.6 x 3.5 mm), pb-free standard commercial CY7C199CN-15VXC 51-85031 28-pin (300-mil) molded soj, pb-free standard commercial cy7c199cnl-15vxi 51-85031 28-pin (300-mil) mo lded soj, pb-free low power industrial 20 cy7c199cn-20zxi 51-85071 28 tsop i (8 x 13.4 mm), pb-free standard industrial ordering code definitions temperature range: x = c or i c = commercial; i = industrial package type: xx = vx or px or zx vx = 28-lead molded soj (pb-free) px = 28-lead dip (pb-free) zx = 28-lead tsop i (pb-free) speed: xx = 15 ns or 20 ns l = low power cn = 0.25 m technology 99 = 256 k bit density with datawidth 8 bits 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - xx xx 7 99 cn x l [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 14 of 18 package diagrams figure 1. 28-pin tsop i (8 x 13.4 mm), 51-85071 51-85071 *i [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 15 of 18 figure 2. 28-pin (300 mil) molded soj, 51-85031 package diagrams (continued) 51-85031 *d [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 16 of 18 figure 3. 28-pin (300 mil) pdip, 51-85014 package diagrams (continued) 51-85014 *e [+] feedback
cy7c199cn document #: 001-06435 rev. *e page 17 of 18 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory soj small outline j-lead tsop thin small outline package vfbga very fine-pitch ball grid array symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes mv milli volts mw milli watts mhz mega hertz pf pico farad c degree celcius wwatts [+] feedback
document #: 001-06435 rev. *e revised march 17, 2011 page 18 of 18 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c199cn ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: cy7c199cn, 256 k (32 k 8) static ram document number: 001-06435 revision ecn. submission date orig. of change description of change ** 430363 see ecn nxr new data sheet *a 684342 see ecn vkn added automotive-a information updated ordering information table *b 839904 see ecn vkn added t doe spec for automotive-a part in ac electrical characteristics table *c 2896044 03/19/2010 nxr updated ordering information table updated package diagram *d 3108898 12/13/2010 pras added ordering code definitions . *e 3198636 03/17/11 pras dislodged automotive device information to 001-67737 updated template and styles. [+] feedback

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